Memory device and method of manufacturing including deuterated oxynitride charge trapping structure

ABSTRACT

A method for manufacturing a charge storage stack including a bottom dielectric layer, a charge trapping structure on the bottom dielectric layer, and a top dielectric layer, each comprising silicon oxynitride, are formed using reactant gases that comprise hydrogen, where the hydrogen comprises at least 90 percent deuterium isotope. The bottom dielectric layer, charge trapping structure, and top dielectric layer each have respective relative concentrations of oxygen and nitrogen. The relative concentration of nitrogen in the charge trapping structure is high enough for the material to act as a charge trapping structure with an energy gap that is lower than the energy gaps in the bottom dielectric layer and the top dielectric layer. The presence of oxygen in the charge trapping structure reduces the number of available dangling bonding sites, and thereby reduces the number of hydrogen inclusions in the structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to nonvolatile memory devices and methodsfor manufacturing such devices.

2. Description of Related Art

Electrically programmable and erasable nonvolatile memory technologiesbased on charge storage structures known as EEPROM and flash memory areused in a variety of modern applications. A number of memory cellstructures are used for EEPROM and flash memory. As the dimensions ofintegrated circuits shrink, greater interest is arising for memory cellstructures based on charge trapping dielectric layers, because of thescalability and simplicity of the manufacturing processes. Memory cellstructures based on charge trapping dielectric layers include structuresknown by the industry names NROM, SONOS, and PHINES, for example. Thesememory cell structures store data by trapping charge in a chargetrapping dielectric layer, such as silicon nitride. As negative chargeis trapped, the threshold voltage of the memory cell increases. Thethreshold voltage of the memory cell is reduced by removing negativecharge from the charge trapping layer.

Conventional SONOS devices use ultra-thin bottom oxide, e.g. less than 3nanometers, and a bias arrangement that causes direct tunneling forchannel erase. Although the erase speed is fast using this technique,the charge retention is poor due to the charge leakage throughultra-thin bottom oxide.

NROM devices use a relatively thick bottom oxide, e.g. greater than 3nanometers, and typically about 5 to 9 nanometers, to prevent chargeloss. Instead of direct tunneling, band-to-band tunneling induced hothole injection BTBTHH can be used to erase the cell. However, the hothole injection causes oxide damage, leading to charge loss in the highthreshold cell and charge gain in the low threshold cell.

In addition, charge trapping memory devices capture electrons in acharge trapping layer in both shallow and deep energy levels. Electronstrapped in shallow levels tend to de-trap faster than those electrons indeeper energy level traps. The shallow level electrons are a significantsource of charge retention problems. In order to keep good chargeretention, deeply trapped electrons are preferred.

For commercial products it is desirable for such devices to hold datafor at least ten years without loss. However, leakage of trapped charge,from shallower and deeper traps both, occurs in such devices due todefects in the materials which accumulate over long use, or which areinherent in the structures. One known class of defects in chargetrapping structures is hydrogen inclusions in dielectric layers andstructures. The hydrogen inclusion occupies a weak bond in a siliconmaterial, such as silicon dioxide and silicon nitride, and candissociate from the lattice structure of the dielectric and become acharge carrier, which then can contribute to charge loss. FIG. 1provides a graphical representation of a typical memory cell based oncharge trapping structures. The memory cell comprises a terminal 10acting as a source, a terminal 11 acting as a drain and a channel region12 in the substrate. A bottom dielectric layer 13 overlies the channelregion 12 and portions of the source and drain terminals 10, 11. Acharge trapping layer 14 overlies the bottom dielectric and a topdielectric 15 overlies the charge trapping layer 14. A gate electrodecomprising a polysilicon layer 16 and a silicide layer 17 lie over thetop dielectric layer 15. A small region of the bottom dielectric layer13, charge trapping layer 14 and top dielectric layer are expandedheuristically in the region 20 on the drawing. Silicon atoms are shownschematically with four lines representing the valence electronsnormally available for bonding, including the three pronged linescoupled on one side of the Si symbols, with one prong on the other side.Most of the bonding sites are occupied in the top and bottom dielectricsby oxygen. However, some hydrogen atoms attach to dangling bonding sitesin the lattice structure, becoming trapped hydrogen inclusions in thedielectric, illustrated by the H in a circle. In the charge trappinglayer 14, most of the bonding sites are occupied by nitrogen, with somehydrogen inclusions.

A number of investigators have looked at replacing hydrogen inclusionswith deuterium isotopes of hydrogen, which form stronger bonds withsilicon and do not dissociate and become charge carriers as easily. Seefor example U.S. Pat. No. 6,670,241 entitled SEMICONDUCTOR MEMORY WITHDEUTERATED MATERIALS, by Kamal et al. Kamal et al. suggests that the topand bottom oxides in an ONO charge trapping layer, as well as overlyingstructures such as polysilicon wordlines, and the silicon nitride chargetrap, all of which contain silicon, can be “deuterated” to improvecharge retention characteristics of the memory cell. (See, column 5,lines 56–61, and column 4, lines 43–52.) However, improved processes andstructures are desirable which can be applied to very small devices, andachieve long retention times.

SUMMARY OF THE INVENTION

The present invention provides a method for manufacturing a chargestorage stack with improved data retention characteristics, applicablefor use in very small memory devices. The method includes the formationof a stack including a bottom dielectric layer, a charge trappingstructure on the bottom dielectric layer, and a top dielectric layer.The bottom dielectric layer, the charge trapping structure, and the topdielectric layer each comprise silicon oxynitride, and are formed usingreactant gases that comprise hydrogen, where the hydrogen comprises atleast 90 percent deuterium isotope. The bottom dielectric layer, chargetrapping structure, and top dielectric layer include hydrogen inclusionswhich can be described for the purposes of description as being attachedto dangling silicon bonding sites that result from manufacturingprocesses that include reaction gases comprising hydrogen. The bottomdielectric layer, charge trapping structure, and top dielectric layereach have respective relative concentrations of oxygen and nitrogen. Therelative concentrations of nitrogen in the charge trapping structure ishigh enough for the material to act as a charge trapping structure withan energy gap that is lower than the energy gaps in the bottomdielectric layer and the top dielectric layer. The presence of oxygen inthe charge trapping structure reduces the number of available danglingbonding sites, and thereby reduces the number of hydrogen inclusions inthe structure. A combination of utilizing deuterium isotope in thereactant gases and silicon oxynitride as the charge trapping structure,substantially reduces the number of hydrogen inclusions, and of thoseinclusions, reduces the number which are not deuterium isotope.

The top and bottom dielectrics are formed in embodiments of thedescribed process using radical oxidation processes that include in situradical formation, such as in situ steam generation ISSG, resulting inhigh-quality ultrathin layers of oxide, including bottom dielectriclayers less than 7 nanometers thick in some embodiments, and less than 3nanometers thick in other embodiments. The layers of oxide can betreated with, or formed in the presence of, a nitrogen containingmaterial. The nitrogen containing material comprises hydrogen in someembodiments, in which the hydrogen comprises at least 90 percentdeuterium isotope. Use of nitrogen containing oxides in the bottom andtop dielectric layers provides improved resistance to breakdown,including resistance to boron penetration which degrades devicedurability. The use of in situ radical oxidation processes, combinedwith deuterated reactant gas and nitrogen treatments in the top andbottom dielectric further enhances performance of the charge storagestack.

The technology described herein provides a new memory device withimproved durability and charged retention characteristics. A memorydevice comprises the terminal, such as a source or drain having a firstconductivity type in a substrate, the region in the substrate adjacentthe terminal having a second conductivity type, the bottom dielectricover portions of the terminal in the region, the charged storagestructure on the bottom dielectric, and the top dielectric over thecharged storage structure. As mentioned above, the bottom dielectriclayer, the charge trapping structure, and the top dielectric layer eachcomprise silicon oxynitride, and are formed using reactant gases thatcomprise hydrogen, where the hydrogen comprises at least 90 percentdeuterium isotope. The bottom dielectric layer, charge trappingstructure, and top dielectric layer include hydrogen inclusions whichcan be described for the purposes of description as being attached todangling silicon bonding sites that result from manufacturing processesthat include reaction gases comprising hydrogen. The bottom dielectriclayer, charge trapping structure, and top dielectric layer each haverespective relative concentrations of oxygen and nitrogen. The relativeconcentrations of nitrogen in the charge trapping structure is highenough for the material to act as a charge trapping structure with anenergy gap that is lower at the interfaces between the layers in thestack, than the energy gaps at the interfaces in the bottom dielectriclayer and in the top dielectric layer.

Other aspects and advantages of the present invention can be seen onreview of the drawings, the detailed description and the claims, whichfollow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagram of a prior art memory device withhydrogen inclusions.

FIG. 2 is a diagram of a memory device including a stack of siliconoxynitride layers with hydrogen inclusions that comprise deuteriumisotope, configured as a charge storage device.

FIG. 3 is a flowchart of a representative process for manufacturing amemory device like that shown in FIG. 2.

FIG. 4 is a flowchart of another representative process formanufacturing a memory device like that shown in FIG. 2.

DETAILED DESCRIPTION

A detailed description of embodiments of the present invention isprovided with reference to the FIGS. 2, 3 and 4.

FIG. 2 provides a graphical representation of a memory cell based on acharge storage stack comprising deuterated oxynitride layers. The memorycell comprises a terminal 50 acting as a source, a terminal 51 acting asa drain and a channel region 52 in the substrate. A bottom dielectriclayer 53 overlies the channel region 52 and portions of the source anddrain terminals 50, 51. A charge trapping layer 54 overlies the bottomdielectric and a top dielectric 55 overlies the charge trapping layer54. A gate electrode comprising a polysilicon layer 56 and a silicidelayer 57 lie over the top dielectric layer 55. A small region of thebottom dielectric layer 53, charge trapping layer 54 and top dielectriclayer are expanded heuristically in the region 60 on the drawing.Silicon atoms are shown schematically with four lines representing thevalence electrons normally available for bonding, including the threepronged lines coupled on one side of the Si symbols, with one prong onthe other side. Most of the bonding sites are occupied in the top andbottom dielectrics by oxygen, with a number of bonding sites occupied bynitrogen. However, some hydrogen atoms, consisting of deuterium isotope,attach to dangling bonding sites in the lattice structure, becomingtrapped hydrogen inclusions in the dielectric, illustrated by the D in acircle. In the charge trapping layer 54, most of the bonding sites areoccupied by nitrogen, with a number of bonding sites occupied by oxygen.Some hydrogen inclusions that consist of deuterium isotope are trappedin the top and bottom dielectrics. The bottom dielectric layer, chargetrapping structure, and top dielectric layer each have respectiverelative concentrations of oxygen and nitrogen. The ratio ofconcentrations of nitrogen to oxygen in the charge trapping structure ishigh enough for the material to act as a charge trapping structure withan energy gap that is lower at the interfaces between the layers in thestack, than the energy gaps at the interfaces in the bottom dielectriclayer and in the top dielectric layer.

FIG. 3 is a simplified flow chart for a manufacturing process for adeuterated oxynitride charge storage stack. The flow chart begins withpreparing the substrate for bottom oxide formation (block 100),according to well known procedures that depend on a particularmanufacturing flow, including, for a couple of examples, definition ofsource and drain terminals, removal of sacrificial oxides, and othersteps leading up to bottom oxide formation. Next the tunnel dielectriclayer acting as the bottom dielectric in the charge storage stack isformed (block 101) using an in situ radical oxidation procedure such asin situ steam generation ISSG. Embodiments of bottom oxide formationprocesses include radical formation according to a formulaD₂+O₂->O*+OD*, caused by introducing a mixture of deuterium D₂ andoxygen O₂ into a reaction chamber under relatively low pressure (lessthan 100 torr for example) with a temperature at the substrate betweenabout 850 and 1150 degrees C, where reactant oxygen O* and hydroxyl OD*radicals are formed, and react with the substrate to form high qualitysilicon oxide. The ratio of concentrations D₂/(D₂+O₂) can be in a rangeup to about 0.4, for a 40% D₂ concentration in the mixture. In oneembodiment the reaction chamber comprises a rapid thermal process RTPtype chamber, as applied for ISSG processes.

After bottom oxide formation, the dielectric layer is annealed in thepresence of a nitrogen source and a source of deuterium, such asammonium or ammonia, where the hydrogen atoms consist essentially ofdeuterium isotope (block 102). Alternative nitrogen sources include N₂and N₂O. Alternative deuterium sources include D₂. The annealing processresults in incorporation of a relatively small concentration of nitrogenatoms in the bottom dielectric layer.

Next, the charge trapping layer is formed (block 103). The chargetrapping layer comprises silicon oxynitride with a relatively highconcentration of nitrogen. An approach to manufacturing the chargetrapping layer includes introducing a mixture of reactant gasesincluding nitrogen, silicon, oxygen and deuterium sources into chamber.In one example the reactant gases include nitrogen oxide N₂O, ammonia,and silane or a silane derivative at a relatively low pressure (e.g.less than 400 torr using a rapid thermal chemical vapor deposition CVDchamber or other single-wafer CVD chamber) at a temperature on thesubstrate of between about 650 and 850 degrees C. For example,N₂O+ND₃+SiD₂Cl₂ or SiD₄ yields SiO_(x)N_(y)+some bi-products in thisenvironment. The gas flow ratio is adjusted to achieve the desiredconcentrations of Si, O and N in the oxynitride layer. To act as acharge trapping layer the concentration of nitrogen in the SiO_(x)N_(y)is significant, and in some embodiments y is much greater than x, sothat the layer approaches a silicon nitride with some extra bondingsites consumed by oxygen, displacing potential sites for hydrogeninclusions.

The top dielectric layer is formed in the next step (block 104) by insitu generated radical oxidation, as described above with respect to thebottom dielectric layer. The top dielectric layer is then annealed inthe presence of nitrogen and deuterium (block 105) to form a topoxynitride. Processing is then finished (block 106), with subsequentlayer and pattern operations forming the gates, metallization, and soon.

FIG. 4 is a simplified flow chart for another manufacturing process fora deuterated oxynitride charge storage stack. The flow chart begins withpreparing the substrate for bottom oxide formation (block 200),according to well known procedures that depend on a particularmanufacturing flow, including, for a couple of examples, definition ofsource and drain terminals, removal of sacrificial oxides, and othersteps leading up to bottom oxide formation. Next the tunnel dielectriclayer acting as the bottom dielectric in the charge storage stack isformed (block 201) introducing a mixture of deuterium D₂ and oxygen O₂into a furnace to form D₂O with a temperature at the substratesufficient to cause oxidation of the silicon to form high qualitysilicon oxide. In one embodiment the reaction chamber comprises a rapidthermal process RTP type chamber instead of a furnace.

After bottom oxide formation, the dielectric layer is annealed in thepresence of a nitrogen source and a source of deuterium, such asammonium or ammonia, where the hydrogen atoms consist essentially ofdeuterium isotope (block 202). Alternative nitrogen sources include N₂and N₂O. Alternative deuterium sources include D₂. The annealing processresults in incorporation of a relatively small concentration of nitrogenatoms in the bottom dielectric layer.

Next, the charge trapping layer is formed (block 203), using processesdescribed above with reference to step 103 of FIG. 3. The chargetrapping layer comprises silicon oxynitride with a relatively highconcentration of nitrogen.

The top dielectric layer is formed in the next step (block 204) by D₂Ooxidation of the silicon oxynitride charge trapping layer. The processapplied is like that described above with respect to the bottomdielectric layer. The top dielectric layer is then annealed in thepresence of nitrogen and deuterium (block 205) to form a top oxynitride.Processing is then finished (block 206), with subsequent layer andpattern operations forming the gates, metallization, and so on.

The commercial gases SiD₄, SiD₂Cl₂, ND₃, or D₂ are considered almost“pure” deuterium. Thus, the hydrogen isotope is considered to be almostabsent in the commercial gases. In embodiments of the processesdescribed herein, a silane mixture including for example, 10%, or less,SiH4 with at least 90% SiD₄ might be used, although greater purity ofdeuterium sources is desirable in other embodiments. For the purpose ofthis description, the hydrogen in the reactant gases consistsessentially of deuterium isotope, the hydrogen in a gas mixture isconsidered to consist essentially of deuterium isotope, if hydrogenatoms in the gas mixture include at least 90% deuterium, with 10%, orless, other isotopes of hydrogen.

While the present invention is disclosed by reference to the preferredembodiments and examples detailed above, it is to be understood thatthese examples are intended in an illustrative rather than in a limitingsense. It is contemplated that modifications and combinations willreadily occur to those skilled in the art, which modifications andcombinations will be within the spirit of the invention and the scope ofthe following claims.

1. A method of manufacturing a charge storage structure for anintegrated circuit memory device, the method comprising: forming abottom dielectric layer by oxidizing silicon by exposure of the siliconto oxidizing radicals, including in situ formation of radicalscomprising hydrogen, wherein the hydrogen comprises at least 90%deuterium isotope; forming a charge trapping structure on the bottomdielectric layer, comprising silicon oxynitride utilizing a reactant gascomprising hydrogen, wherein the hydrogen comprises at least 90%deuterium isotope, and forming a top dielectric layer on the chargetrapping layer by oxidizing silicon by exposure of the silicon tooxidizing radicals, including in situ formation of radicals comprisinghydrogen, wherein the hydrogen comprises at least 90% deuterium isotope.2. The method of claim 1, wherein the charge trapping structurecomprises silicon nitride, and said forming a top dielectric layercomprises oxidation using in situ steam generation ISSG, and whereinsaid radicals comprise OD, where D is the deuterium isotope of hydrogen.3. The method of claim 1, wherein said forming a charge trappingstructure comprises deposition of silicon oxynitride, and said reactantgas comprises at least one of a silane and a silane derivative.
 4. Themethod of claim 1, wherein said forming a charge trapping structurecomprises deposition of silicon oxynitride, and said reactant gascomprises at least one of ammonia and ammonium.
 5. The method of claim1, wherein said forming a top dielectric layer comprises exposing thetop dielectric layer to a nitrogen containing reactant gas.
 6. Themethod of claim 1, wherein said forming a top dielectric layer comprisesexposing the top dielectric layer to a reactant gas including at leastone of ammonia and ammonium with hydrogen atoms in the reactant gasconsisting essentially of deuterium isotope.
 7. The method of claim 1,wherein the bottom dielectric layer is formed on a substrate comprisingsilicon, and said forming a bottom dielectric layer comprises oxidationof the substrate using in situ steam generation ISSG in the presence ofa reactant gas comprising OD, where D is the deuterium isotope ofhydrogen.
 8. The method of claim 1, wherein the charge trappingstructure has a sufficient concentration of nitrogen relative to oxygento act as a charge trapping structure for a memory device, and thebottom dielectric and top dielectric layers comprise silicon oxynitride,having respective concentrations of nitrogen relative to oxygen that areless than said sufficient concentration.
 9. A method of manufacturing acharge storage structure for an integrated circuit memory device, themethod comprising: forming a bottom dielectric layer by oxidizing thesubstrate; forming a charge trapping structure on the bottom dielectriclayer comprising silicon oxynitride utilizing a reactant gas comprisinghydrogen, wherein the hydrogen comprises at least 90% deuterium isotope,and forming a top dielectric layer on the charge trapping layer byoxidizing silicon by exposure of the silicon to water at a temperaturesufficient for oxidation, wherein hydrogen atoms in the water compriseat least 90% deuterium isotope.
 10. The method of claim 9, wherein saidforming a charge trapping structure comprises deposition of siliconoxynitride, and said reactant gas comprises at least one of a silane anda silane derivative.
 11. The method of claim 9, wherein said forming acharge trapping structure comprises deposition of silicon oxynitride,and said reactant gas comprises at least one of ammonia and ammonium.12. The method of claim 9, wherein said forming a top dielectric layercomprises exposing the top dielectric layer to a nitrogen containingreactant gas.
 13. The method of claim 9, wherein said forming a topdielectric layer comprises exposing the top dielectric layer to areactant gas including at least one of ammonia and ammonium withhydrogen atoms in the reactant gas consisting essentially of deuteriumisotope.
 14. The method of claim 9, wherein the bottom dielectric layeris formed on a substrate comprising silicon, and said forming a bottomdielectric layer comprises oxidizing silicon by exposure of the siliconto water at a temperature sufficient for oxidation, wherein hydrogenatoms in the water comprise at least 90% deuterium isotope.
 15. Themethod of claim 9, wherein the charge trapping structure has asufficient concentration of nitrogen relative to oxygen to act as acharge trapping structure for a memory device, and the bottom dielectricand top dielectric layers comprise silicon oxynitride, having respectiveconcentrations of nitrogen relative to oxygen that are less than saidsufficient concentration.